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HT82V24
16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor
Features
* Operating voltage: 5V * Low power consumption at 380mW (Typ.) * Power-down mode: Under 2mA (Typ.) * 16-bit 15 MSPS A/D converter * Supports ADI/WM mode data output formats selec* Input clamp circuitry * Internal voltage reference * Multiplexed byte/nibble-wide output (82/44 format) * Programmable 3-wire serial interface * 3V/5V digital I/O compatibility * 3-channel operation up to 5 MSPS for each channel * 2-channel (Even-Odd) operation up to 7.5 MSPS for
tion
* Guaranteed wont miss codes * 1~6x programmable gain * Correlated Double Sampling * 300mV programmable offset
each channel
* 1-channel operation up to 15 MSPS * 20/28-pin SOP/SSOP package (Pb-free on request)
Applications
Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals
General Description
The HT82V24 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of tri-linear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), and a high performance 16-bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output is multiplexed into an 8/4-bit output word that is accessed using two/four read cycles. The internal registers are programmed through a 3-wire serial interface, which provides gain, offset and operating mode adjustments. HT82V24 supports ADI/WM mode data output formats. The HT82V24 operates from a single 5V power supply, typically consumes 380mW of power.
Block Diagram
AVDD AVSS REFT REFB AVDD AVSS DVDD DVSS
V IN R
CDS
+ 9 - B it DAC
PGA BANDGAP R e fe re n c e PGA 3 .1 MUX 1 6 - B it ADC C o n fig u r a tio n R e g is te r MUX R e g is te r 6 RED GREEN BLUE D ig ita l C o n tro l In te rfa c e 16 MUX 8 or4
OE
V IN G
CDS
+ 9 - B it DAC
DOUT
V IN B
CDS
+ 9 - B it DAC 9
PGA
OFFSET
In p u t C la m p B ia s
G a in R e g is te r s
SC LK SLO AD SDATA
RED GREEN BLUE
O ffs e t R e g is te r s AD CCLK
C D S C L K 1 /V S M P
CDSCLK2
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HT82V24
Pin Assignment
C D S C L K 1 /V S M P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CDSCLK2 AD CCLK OE AVSS 1 2 3 4 5 6 7 8 9 10 AVDD VSMP AD CCLK DVDD DVSS D7 D6 D5 D4 20 19 18 17 16 15 14 13 12 11 V IN R OFFSET CML REFT REFB AVSS AVDD SLO AD SC LK SDATA DVDD DVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B ) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
H T82V24 2 0 S O P -A /S S O P -A
H T82V24 2 8 S O P -A /S S O P -A
Pin Description
Pin Name CDSCLK1/VSMP CDSCLK2 ADCCLK OE DVDD DVSS D7~D0 SDATA SCLK SLOAD AVSS AVDD REFB REFT VINB CML VING OFFSET VINR I/O DI DI DI DI P P DO DI DI P P AO AO AI AO AI AO AI CDS reference clock pulse input ADI mode: CDSCLK1 WM mode: VSMP CDS data clock pulse input A/D sample clock input for 3-channels mode Output enable, active low Digital power Digital ground Digital data output Clock input for serial interface Serial interface load pulse Analog ground Analog supply Reference decoupling Reference decoupling Analog input, blue Internal reference output Analog input, green Clamp bias level decoupling Analog input, red Description
DI/DO Serial data input/output
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT82V24
D.C. Characteristics
Symbol Logic Inputs VIH VIL IIH IIL CIN VOH VOL IOH IOL High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5V 5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.8DVDD 3/4 3/4 3/4 3/4 DVDD-0.5 3/4 3/4 3/4 3/4 3/4 10 10 10 3/4 3/4 0.7 1.1 3/4 0.2DVDD 3/4 3/4 3/4 3/4 0.5 3/4 3/4 V V mA mA pF V V mA mA Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Logic Outputs
A.C. Characteristics
Symbol Power Supplies AVDD DVDD Analog Power Digital I/O Power 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 4.75 3 5 5 5.25 5.25 V V Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Maximum Conversion Rate fMAX3 fMAX2 fMAX1 3-channel Mode with CDS 2-channel Mode with CDS 1-channel Mode with CDS 15 15 15 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 150 3/4 3/4 AVDD+0.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MSPS MSPS MSPS
Accuracy (Entire Signal Path) ADC Resolution Integral Nonlinear (INL) Differential Nonlinear (DNL) Offset Error Gain Error Analog Inputs RFS Vi Ci Ii Amplifiers PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution Programmable Offset at Minimum Programmable Offset at Maximum Offset Resolution 3/4 3/4 3/4 3/4 3/4 3/4 1 6 6 -300 300 9 V/V V/V Bits mV mV Bits Full-scale Input Range Input Limits Input Capacitance Input Current 3/4 AVSS-0.3 3/4 3/4 2.0/3.0* 3/4 10 10 Vp-p V pF nA 3/4 3/4 -1 -150 3/4 16 32 3/4 3/4 5 Bits LSB LSB mV %FSR
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Symbol Temperature Range tA Operating 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 3/4 70 C Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Power Consumption Ptot3 Ptot2 Ptot1 Total Power Consumption (3CH) Total Power Consumption (2CH) Total Power Consumption (1CH) 3/4 3/4 3/4 380 340 300 3/4 3/4 3/4 mW mW mW
Note: * means the full-scale input range select by configuration register Timing Specification Symbol Clock Parameters tPRA tPRB tPRC tADCLK tC1 tC2 tC1C2 tADC2 tC2ADR tC2ADF tC2C1 tAD 3-channel pixel rate 2-channel (Even-Odd) pixel rate 1-channel pixel rate ADCCLK Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Rising to CDSCLK2 Falling CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling to ADCCLK Falling CDSCLK2 Falling to CDSCLK1 Rising Analog Sampling Delay 200 133 66 33 15 15 0 0 5 30 30 3/4 3/4 3/4 3/4 3/4 30 30 3/4 3/4 3/4 3/4 3/4 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. Typ. Max. Unit
Serial Interface fSCLK tLS tLH tDS tDH tRDV Data Output tOD Output Delay 3/4 12 ns Maximum SCLK Frequency SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Setup Time SCLK Rising to SDATA Hold Time Falling to SDATA Valid 10 10 10 10 10 10 3/4 3/4 3/4 3/4 3/4 3/4 MHz ns ns ns ns ns
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HT82V24
Functional Description
Integral Nonlinear (INL) Integral nonlinear error refers to the deviation of each individual code from a line drawn from zero scale through a positive full scale. The point used as zero scale occurs 1/2 LSB before the first code transition. A positive full scale is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinear (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed for the 16-bit resolution indicates that all the 65536 codes respectively, are present in the over-all operating range. Offset Error The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. Internal Register Descriptions Register Name Configuration Address A2 0 A1 0 A0 0 D8 0 D7 D6 D5 Data Bits D4 D3 Clamp Voltage 0 D2 D1 D0 Enable Input 1 byte Power Range out Down 0 0 0 LSB LSB LSB LSB LSB LSB The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value of 1/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and the last code transitions and the ideal difference between the first and the last code transitions. Sampling Delay The sampling delay is the time delay that occurs when a sampling edge is applied to the HT82V24 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the sampling delay is measured from each clocks falling edge to the instant the actual internal sample is taken.
Dont care RGB/ BGR 0 0 0
3-CH CDS on
MUX Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
0 0 0 0 MSB MSB MSB
Red 0 0 0
Green MSB MSB MSB
Blue
Internal Register Map (ADI Mode) Register Name Configuration Address A2 0 A1 0 A0 0 D8 1 D7 D6 D5 Data Bits D4 D3 Clamp Voltage D2 D1 D0 Enable Input Output Power Range Format Down VDEL LSB LSB LSB LSB LSB LSB
Clamp Timing 3-CH CDS on Control RGB/ BGR 0 0 0 Red 0 0 0 Green MSB MSB MSB
MUX Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
DEL 0 0 0 MSB MSB MSB
Blue POSNNEG
Internal Register Map (Wolfson Mode)
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HT82V24
Configuration Register The configuration register controls the HT82V24s operating mode and bias levels. Bits D7 and D6 set the clamp timing in WM mode and there are don't care in ADI Mode. Bit D5 will configure the HT82V24 for the 3-channel (high) mode of operation. Setting the bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 sets the dc bias level of the HT82V24s input clamp. This bit should always be set high for the 4V D8 D7 D6 D5 D4 clamp bias, unless a CCD with a reset feed through transient exceeding 2V is used. Setting the bit D3 low, the clamp voltage is 3V. Bit D2 controls the power-down mode. Setting bit D2 high will place the HT82V24 into a very low power sleep mode. All register contents are retained while the HT82V24 is in the power-down state. Setting bit D1 high will select the 3V input range, otherwise the 2V input range is selected.
D3
D2 Power-down 1=On 0=Off (Normal)*
D1 Input Range 1=3V 0=2V*
D0 1 byte out (High-byte only) 1=On 0=Off*
3 channels CDS operation Clamp bias Set to 0 Dont care 1=On* 0=Off 1=CDS mode* 0=SHA mode 1=4V* 0=3V
Configuration Register Settings (ADI Mode) D8 D7 D6 D5 D4 D3 D2 Power-down 1=On 0=Off (Normal)* D1 Input Range 1=3V 0=2V* D0 Output Format 1=Byte output 0=Nibble output*,**
Clamp Timing Control 3 channels CDS operation Clamp bias Set to 1 CDSREF1 CDSREF0 0* 0* 1=On* 0=Off 1=CDS mode* 0=SHA mode 1=4V* 0=3V
Configuration Register Settings (Wolfson Mode) Note: * Power-on default value ** It needs D5=0, D0=0 to enable Nibble output (1CH WM mode) Bits D7 and D6 control the reset sample and clamp timing
AD C C LK
VSMP
R S /C L CDSREF=00 R S /C L CDSREF=01
R S /C L CDSREF=10 R S /C L CDSREF=11
Reset Sample and Clamp Timing (RS/CL) Note: CDSREF=(CDSREF1,CDSREF0)
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HT82V24
Bit D0 control the ADC output cycle of the HT82V24. Bit D8 selects the ADC data output format selection. Setting D8 high enables the WM mode data output format while setting bit D8 low enables the ADI mode output data format. The one nibble data will output data to pins D7~D4 and 44 (WM) mode output the data format selected. The output format as the following table: D8 0 0 1 1 D0 0 1 0 1 ADC Output Format D5=1: 3-CH 82 (ADI) D5=0: 1 or 2-CH 82 (ADI) D5=1: 3-CH 81 (ADI) D5=0: 1 or 2-CH 81 (ADI) D5=0: 1-CH 44 (WM) D5=1: 3-CH 82 (WM) D5=0: 1-CH 82 (WM)
AD CC LK
AD CC LK
O u tp u t D a ta D 7~D4
A H ig h N ib b le
B
C
D Low N ib b le
O u tp u t D a ta D 7~D0
A1 H ig h B y te
B1 Low B y te
A2
B2
4 x 4 (W M ) O u tp u t D a ta F o rm a t
8 x 2 (A D I) O u tp u t D a ta F o r m a t
AD CC LK
AD CC LK
O u tp u t D a ta D 7~D0 A
B L o w B y te
O u tp u t D a ta D 7~D0
A1 H ig h B y te
A2 H ig h B y te
H ig h B y te
8 x 2 (W M ) O u tp u t D a ta F o rm a t
8 x 1 (A D I) O u tp u t D a ta F o r m a t
MUX Register The MUX register controls the sampling channel order and the 2-channel mode configuration in the HT82V24. Bit D8 is used to set the output latency in ADC clock period and is only valid when WM mode data output format is selected. Bit D7 is used when operating in the 3-channel mode or the 2-channel mode. Setting bit D7 high will sequence the MUX to sample the red channel first, then the green channel, and then the blue channel. When in the 3-channel mode, the CDSCLK2 rising edge always resets the MUX to sample the red channel first (see timing diagrams). When bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 rising edge will always reset the D8 D7 MUX Order Set to 0 1=R-G-B* 0=B-G-R 1=RED* 0=Off D6 D5 Channel Select 1=GREEN 0=Off* 1=BLUE 0=Off* Set to 0 D4 MUX to sample the blue channel first. Bits D6, D5 and D4 are used when operating in 1 or 2-channel mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX will remain stationary during 1-channel mode. The two channel mode is selected by setting two of the channel select bits (D4~D6) high. The MUX samples the channels in the order selected by bit D7. In WM mode, Bits D0~D2 are used to control the sampling point delay option. Bit D3 is used to select the rising or falling edge on the CDSCLK1 input pin and generates an internal VSMP pulse. Bits D0~D3 set to 0 in ADI Mode. D3 D2 D1 D0
MUX Register Settings (ADI Mode)
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HT82V24
D8 DEL D7 MUX Order D6 D5 Channel Select D4 D3 D2 D1 D0
CDS Edge Detection Select Delay Period Select POSNNEG 0* VDEL VDEL VDEL 2 1 0 0* 0* 0*
1: Delay by two ADC 1=R-G-B* 1=RED* 1=GREEN 1=BLUE clock 0: Minimum latency* 0=B-G-R 0=Off 0=Off* 0=Off*
MUX Register Settings (Wolfson Mode) Note: * Power-on default value D0~D3 and D8 are valid only at WM mode.
AD CCLK
VSMP
PO SNNEG =1 (V D E L = 0 0 0 ) IN T V S M P V
S
V
S
V
S
(V D E L = 0 0 1 ) IN T V S M P V (V D E L = 0 1 0 ) IN T V S M P
S
V
S
V
S
V
S
V
S
V
S
(V D E L = 0 1 1 ) IN T V S M P V (V D E L = 1 0 0 ) IN T V S M P V
S
S
V
S
V
S
V
S
V
S
(V D E L = 1 0 1 ) IN T V S M P V (V D E L = 1 1 0 ) IN T V S M P
S
V
S
V
S
V
S
V
S
V
S
(V D E L = 1 1 1 ) IN T V S M P V
S
V
S
V
S
PO SNNEG =0 (V D E L = 0 0 0 ) IN T V S M P (V D E L = 0 0 1 ) IN T V S M P (V D E L = 0 1 0 ) IN T V S M P (V D E L = 0 1 1 ) IN T V S M P (V D E L = 1 0 0 ) IN T V S M P (V D E L = 1 0 1 ) IN T V S M P (V D E L = 1 1 0 ) IN T V S M P (V D E L = 1 1 1 ) IN T V S M P V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
Note: VDEL=(VDEL2, VDEL1, VDEL0)
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HT82V24
PGA Gain Registers There are three PGA registers for use in individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See figure for a graph of the PGA gain versus PGA register code. The coding for the PGA registers is a straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (6x). The HT82V24 uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1x (0dB) to 6x (15.6dB), adjustable in 64 steps. The Figure shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in nonlinear proportion with the register code, according to the following the 6 equation: Gain= 63 - G 1+ 4.85x( ) 63
0
Where G is the decimal value of the gain register contents, and varies from 0 to 63.
16 12 ) 9 G A IN -d B ( 6 3 6 5 .0 4 .0 3 .0 2 .0 1 .0 G A IN -V /V ( )
PGA Gain Transfer Function
D8 Set to 0 0 0
D7 Set to 0 0 0
D6 Set to 0 0 0
D5 MSB 0 0
D4
D3
D2
D1
D0 LSB
Gain (V/V)
Gain (dB)
0 0
0 0
0 0
0 0
1 1
1 1
0 0 . . . 1 1
0 0
0 0
0* 1
1 1
1 1
0 1
1.0 1.039 . . . 5.57 6
0.0 0.33 . . . 14.9 15.6
PGA Gain Register Settings Note: * Power-on default value Offset Registers There are three offset registers for use in individually programming the offset in the red, green, and blue channels. Bits D8 through D0 control the offset range from -300mV to 300mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. The following table shows the offset range as a function of the bits D8 through D0. D8 MSB 0 0 0 0 0 0 0 0 0 0 0 0 . . . 1 0 0 . . . 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB 0* 1 0 1.17 . . . 300 0 -1.17 . . . -300 Offset (mV)
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1
1
1
1
1
1
1
1
Note: * Power-on default value
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HT82V24
Timing Diagrams
SDATA SC LK tL
S
R /W b
tD
H
A2
A1
A0
tD
S
D8
D7
D6
D5
D4
D3
D2
D1
D0
tL
H
SLO AD
Serial Write Operation Timing
SDATA SC LK tL
S
R /W b
A2
A1
A0
D8
tR
D7
DV
D6
D5
D4
D3
D2
D1
D0
tL
H
SLO AD
Serial Read Operation Timing Part (A): 82 (ADI) Output Format
A n a lo g In p u t (R , G , B )
P ix e l ( N + 2 ) tA
D
P ix e l ( N + 3 )
P ix e l ( N + 4 )
tC
1
tA
D
tC
2C1
tP
RA
CDSCLK1
tC
1C2
tC
2
CDSCLK2 tA AD CCLK tA O u tp u t D a ta D7~D0
R (N -2 ) G (N -2 ) G (N -2 )
D CLK D CLK
tC
2ADF
tA
DC2
tC
2ADR
tO
D
tO
D
B (N -2 )
B (N -2 )
R (N -1 )
R (N -1 ) G
(N -1 )
G
(N -1 ) B (N -1 )
B (N -1 )
R (N )
R (N ) G
(N )
G
(N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
3-Channel CDS Mode Timing
A n a lo g In p u t (R , G , B )
P ix e l ( N + 3 ) tA
D
P ix e l ( N + 4 )
P ix e l ( N + 5 )
tC
1
tC
2C1
tP
RA
CDSCLK1
tC
1C2
tC
2
CDSCLK2
tA tC
DC2 2ADR
tC
2ADF
AD CCLK
tA
D CLK
tA
D CLK
O u tp u t D a ta D7~D0
G
(N -2 )
G
(N -2 )
B (N -2 )
B (N -2 )
G
(N -1 )
G
(N -1 )
B (N -1 )
B (N -1 )
G
(N )
G
(N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
2-Channel CDS Mode Timing
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HT82V24
A n a lo g In p u t
P ix e l ( N ) tA
D
P ix e l ( N + 1 )
P ix e l ( N + 2 )
tC
1
tA
D
tC
2C1
tP
RA
CDSCLK1
tC
1C2
tC
2
CDSCLK2 tC AD CCLK tA O u tp u t D a ta D7~D0
P ix e l ( N - 9 ) H ig h B y te
D CLK 2ADR
tC tA
2ADF
D CLK
tO
D
P ix e l ( N - 9 ) L o w B y te
P ix e l ( N - 8 ) H ig h B y te
P ix e l ( N - 8 ) L o w B y te
P ix e l ( N - 7 ) H ig h B y te
P ix e l ( N - 7 ) Low B y te
1-Channel CDS Mode Timing
P ix e l ( N + 2 ) tA
D
A n a lo g In p u t (R , G , B )
P ix e l ( N + 3 )
CDSCLK2
tC
2
tP tC tC
2AD
RA
tA AD CCLK
D CLK
tA
DC2
2ADR
tA O u tp u t D a ta D7~D0
R (N -2 ) G (N -2 ) G (N -2 )
DC LK
tO
D
B (N -2 )
B (N -2 )
R (N -1 )
R (N -1 ) G
(N -1 )
G
(N -1 ) B (N -1 )
B (N -1 )
R (N )
R (N )
G
(N )
G
(N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
3-Channel SHA Mode Timing
P ix e l ( N + 3 )
A n a lo g In p u t (R , G , B )
P ix e l ( N + 4 )
tA
D
tC
2
CDSCLK2
tA tC
DC2 2ADR
tC
2ADF
AD CCLK
tA
D CLK
tA
D CLK
O u tp u t D a ta D7~D0
G
(N -2 )
G
(N -2 )
B (N -2 )
B (N -2 )
G
(N -1 )
G
(N -1 )
B (N -1 )
B (N -1 )
G
(N )
G
(N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
2-Channel SHA Mode Timing
Rev. 1.00
11
September 7, 2005
HT82V24
P ix e l ( N ) P ix e l ( N + 1 )
A n a lo g In p u t
tC
tA
D 2
tP
RB
CDSCLK2 tC AD CCLK tA O u tp u t D a ta D7~D0
P ix e l ( N - 9 ) H ig h B y te
D CLK 2ADR
tC tA
2ADF
D CLK
tO
D
P ix e l ( N - 9 ) Low B y te
P ix e l ( N - 8 ) H ig h B y te
P ix e l ( N - 8 ) Low B y te
P ix e l ( N - 7 ) H ig h B y te
P ix e l ( N - 7 ) Low B y te
1-Channel SHA Mode Timing Part (B): WM Mode Output Format at VDEL=(0,0,0), POSNEG=1 (Those Diagrams are identical for both CDS and SHA Operation)
* 3-CH 82 (WM)
1 6 .5 A D C C L K P e r io d s AD CCLK VSMP A n a lo g In p u t (R , G , B ) O u tp u t D a ta D 7 ~ 8 x 2 (W DEL O u tp u t D a ta D 7 ~ 8 x 2 (W DEL D0 M) =0 D0 M) =1 B
A
R
A
R
B
G
A
G
B
B
A
B
B A
R
A B
R
B
G
A
G
B
B
A
B
B A
R
A B
R
B
G
A
G
B
B
A
B
B A
R
A B
R
B
G
A
G
B
B
A
B
B A
R
A B
R
B
G
A
G
B
B
A
B
B A
B
B
R
A
R
B
G
G
B
A
B
B
R
A
R
B
G
G
B
A
B
B
R
A
R
B
G
G
B
A
B
B
R
A
R
B
G
G
B
A
B
B
R
A
R
B
G
G
B
3-Channel Mode Timing (Select R-G-B Mode)
* 1-CH 82 (WM)
1 6 .5 A D C C L K P e r io d s AD CCLK VSMP A n a lo g In p u t (R , G , B ) O u tp u t D a ta D 7 ~ 8 x 2 (W DEL O u tp u t D a ta D 7 ~ 8 x 2 (W DEL D0 M) =0 D0 M) =1 R
A
R
B
x R
A
x R
B
x x
x x
R
A
R
B
x R
A
x R
B
x x
x x
R
A
R
B
x R
A
x R
B
x x
x R x
A
R
B
x R
A
x R
B
x x x
x
R
A
R
B
x
x
x
x
x
x
x
x
x
x
1-Channel Mode Timing (Select R Mode)
* 1-CH 44 (WM)
1 6 .5 A D C C L K P e r io d s AD CCLK VSMP A n a lo g In p u t ( R ) O u tp u t D a ta D 7 ~ 4 x 4 (W DEL O u tp u t D a ta D 7 ~ 4 x 4 (W DEL D4 M)A =0 D4 M) =1 B D C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
1-Channel Mode Timing (Select R Mode)
Rev. 1.00
12
September 7, 2005
HT82V24
Application Circuits
The recommended circuit configuration for the 3-channel CDS mode operation is shown in the figure below (ADI mode data output format). The recommended input coupling capacitor value is 0.1mF. A single ground plane is recommended for the HT82V24. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V24. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of the CDSCLK2 should occur in coincidence with or before the rising edge of ADCCLK. All 0.1mF decoupling capacitors should be located as close as possible to the HT82V24 pins. When operating in a single channel mode, the unused analog inputs should be grounded.
V C lo c k In p u ts 1 2 0 .1 m F 0 .1 m F 1 2 3 5 V /3 V 4 5 0 .1 m F 6 7 8 9 10 D a ta O u tp u ts C lo c k In p u ts R e d In p u t AVSS AVDD VSMP AD CCLK DVDD DVSS D7 D6 D5 D4 V IN R OFFSET CML REFT REFB AVSS AVDD SLO AD SC LK SDATA 20 19 18 17 16 15 14 13 12 11 0 .1 m F 1 0 m F 0 .1 m F 5V S e r ia l In p u ts D a ta O u tp u ts 0 .1 m F 0 .1 m F 0 .1 m F 9 10 11 12 13 14 0 .1 m F 1 .0 m F 5 0 .1 m F 6 7 8 3 5 V /3 V 4 V
DD DD
C D S C L K 1 /V S M P CDSCLK2 AD CCLK OE DVDD DVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B )
AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 .1 m F 0 .1 m F 0 .1 m F
0 .1 m F
0 .1 m F 0 .1 m F
R e d In p u t G re e n In p u t B lu e In p u t 1 .0 m F
0 .1 m F 0 .1 m F 1 0 m F 0 .1 m F 5V S e r ia l In p u ts 0 .1 m F
H T 8 2 V 2 4 (C D S M o d e )
H T 8 2 V 2 4 (C D S M o d e )
V C lo c k In p u ts 1 2 R e d In p u t D C Level 0 .1 m F 6 7 0 .1 m F 0 .1 m F 1 0 m F 0 .1 m F 5V S e r ia l In p u ts D a ta O u tp u ts 9 10 11 12 13 14 0 .1 m F 8 3 5 V /3 V 4 5 V 0 .1 m F 1 2 3 5 V /3 V 4 5 0 .1 m F 6 7 8 9 10 D a ta O u tp u ts C lo c k In p u ts
DD
DD
C D S C L K 1 /V S M P CDSCLK2 AD CCLK OE DVDD DVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B )
AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0 .1 m F
R e d In p u t G re e n In p u t B lu e In p u t DC Level
AVSS AVDD VSMP AD CCLK DVDD DVSS D7 D6 D5 D4
V IN R OFFSET CML REFT REFB AVSS AVDD SLO AD SC LK SDATA
20 19 18 17 16 15 14 13 12 11
0 .1 m F
0 .1 m F 0 .1 m F 1 0 m F 0 .1 m F 5V S e r ia l In p u ts 0 .1 m F
H T 8 2 V 2 4 (S H A M o d e )
H T 8 2 V 2 4 (S H A M o d e )
Note:
For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V24 without the use of coupling capacitors. The OFFSET pin should be grounded if the inputs to the HT82V24 are to be referenced to ground, or a DC offset voltage should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs. The analog input signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground.
Rev. 1.00
13
September 7, 2005
HT82V24
Package Information
20-pin SOP (300mil) Outline Dimensions
20
A
11
B
1
C C'
10
G H
D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 490 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 510 104 3/4 3/4 38 12 10
Rev. 1.00
14
September 7, 2005
HT82V24
20-pin SSOP (209mil) Outline Dimensions
20
A
11
B
1
C C'
10
G H
D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 291 196 9 271 65 3/4 4 26 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25.59 3/4 3/4 3/4 3/4 Max. 323 220 15 295 73 3/4 10 34 8 8
Rev. 1.00
15
September 7, 2005
HT82V24
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.00
16
September 7, 2005
HT82V24
28-pin SSOP (209mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 291 196 9 396 65 3/4 4 26 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25.59 3/4 3/4 3/4 3/4 Max. 323 220 15 407 73 3/4 10 34 8 8
Rev. 1.00
17
September 7, 2005
HT82V24
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 20W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
SSOP 20N (209mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 16.8+0.3 -0.2 22.20.2
Rev. 1.00
18
September 7, 2005
HT82V24
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24+0.3 -0.1 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.80.1 13.30.1 3.20.1 0.30.05 21.3
Rev. 1.00
19
September 7, 2005
HT82V24
SSOP 20N (209mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16+0.3 -0.1 120.1 1.750.1 7.50.1 1.5+0.1 1.5+0.25 40.1 20.1 7.10.1 7.20.1 20.1 0.30.05 13.3
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.00
20
September 7, 2005
HT82V24
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
21
September 7, 2005

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